1. Field of the Invention
The invention generally relates to integrated circuits and in particular relates to a high-speed multiple-input complementary metal oxide semi-conductor (CMOS) OR-gate employing a sense amplifier.
2. Description of Related Art
Multiple-input OR-gate circuits are widely used in complex logic integrated circuit chips such as microprocessors and high speed comparators. A conventional multiple-input OR-gate employing five inputs is illustrated in FIG. 1. OR-gate 10 of FIG. 1 includes a set of five PMOS transistors 12.sub.1 -12.sub.5 connected in series and a set of five NMOS transistors 14.sub.1 -14.sub.5 connected in parallel to a common signal line 16. Input signals are received along five input lines i1-i5 with each input line connected to a PMOS transistor and a corresponding NMOS transistor. Specifically, input i1 is connected to both a gate of PMOS transistor 12.sub.1 and a gate of NMOS transistor 14.sub.1. Inputs i2-i5 are respectively connected to gates of PMOS transistors 12.sub.2 -12.sub.5 and gates of NMOS transistors 14.sub.2 -14.sub.5. Sources of each of the NMOS transistors 14 are connected to a ground. Drains of each of the NMOS transistors 14 are connected to common signal line 16. A source of PMOS transistor 12.sub.1 is connected to a voltage line at V.sub.cc. A drain of transistor 12.sub.5 is connected to common signal line 16. The remaining sources and drains of PMOS transistors 12.sub.1 -12.sub.5 are connected in series, as shown. A single inverter 18 is connected to common line 16 for inverting and amplifying signals received along line 16 onto an output line 20 and to create the OR-function of input i1-i5.
Usually, a PMOS transistor must have a size three times greater than an NMOS transistor within the same circuit. With the configuration shown in FIG. 1, wherein the PMOS transistors are connected in series, each of the PMOS transistors must have a size fifteen times greater than that of corresponding NMOS transistors. For example, with each of the PMOS transistors having a channel ratio, defined as channel width over channel length in microns, of 5/0.8, each of the NMOS transistors should have a channel ratio of 75/0.8. As a result, the gate capacitance of the input signal lines is extremely high. Furthermore, because of fabrication constraints, the total silicon area required to achieve a reasonable switching speed using such large PMOS transistors is substantial. An increase in the number of input lines necessitates a corresponding increase in PMOS transistor size, resulting in still higher input gate capacitances and still greater silicon surface area requirements. As can be appreciated, the OR-gate configuration of FIG. 1 becomes less and less feasible with an increasing number of inputs.
To facilitate a greater number of inputs, an OR-gate configuration as illustrated in FIG. 2 has been proposed. FIG. 2 illustrates an OR-gate circuit 30 having a set of NMOS transistors, 32.sub.1 -32.sub.64, each having a source connected to a ground and a drain connected to a common signal line 36. The total of 64 input lines i1-i.sub.64 are provided with each input line connected to a gate of one of the NMOS transistors. Rather than providing a set of PMOS transistors in series, as in the configuration of FIG. 1, the circuit of FIG. 2 includes an additional NMOS transistor 38, a single PMOS transistor 40 and a pair of inverters 42 and 44, all connected along signal line 36. NMOS transistor 38 has a source and drain connected in series along line 36 and a gate connected to a Vcc voltage level. PMOS transistor 40 has a source connected to the Vcc voltage level, a drain connected to signal line 36 and a gate connected to a ground. NMOS transistor 38 is connected along signal line 36 between the input NMOS transistors 32.sub.1 -32.sub.64 and the drain connection of PMOS transistor 40. Further along signal line 36, inverters 42 and 44 are connected in series with an output of inverter 44 connected to an output line 46. Inverters 42 and 44 operate to both invert and amplify signals received along line 36 to provide a buffered OR output along line 46 having the same polarity as input line 36.
As can be seen from FIG. 2, only a single PMOS pull-up transistor is employed. Accordingly, both surface area and input gate capacitance is substantially less than that of the configuration of FIG. 1. For example, with input transistors 32.sub.1 -32.sub.64 each having a channel ratio of 5/0.8, pull-up PMOS transistor 40 may have a channel ratio of 15/0.8--substantially less than the 75/0.8 channel ratio required for each of the PMOS transistors required for the configuration of FIG. 1 which receives only five input lines, rather than sixty-four.
The provision of NMOS transistor 38 reduces an overall voltage swing occurring along signal line 36 by an amount Vtn, where Vtn is the threshold voltage for NMOS transistor 38. The reduction in voltage swing in turn facilitates operation of PMOS transistor 40 in pulling up the voltage along signal line 36 between NMOS transistor 38 and inverter 42 to V.sub.cc.
Although the configuration of FIG. 2 presents a substantial improvement of that of FIG. 1, particularly for multiple-inputs, the circuit configuration of FIG. 2 has several possible disadvantages. A first disadvantage is that, although the size of PMOS transistor 40 is substantially less than that required in the configuration of FIG. 1, the size is still greater than would otherwise be desirable. The fairly large size of PMOS transistor 40 is required to facilitate the pull up of voltage towards V.sub.cc which, in turn, causes a high power dissipation by the overall circuit when any of the NMOS pull-down transistors 32 are active. That is, considerable power dissipation occurs whenever input signals are received along any of the input lines. A second disadvantage of the configuration of FIG. 2 is that a rise time occurring along signal line 36 between NMOS transistors 38 and inverter 42 is relatively slow because PMOS transistor 40 must first operate to pull up the voltage along signal line 36 prior to NMOS transistor 38 to a voltage level of V.sub.cc -Vtn.
Pull-up along line 36 is required before NMOS transistor 38 becomes cut off and allows PMOS transistor 40 to pull up signal line 36 to the V.sub.cc. Thus, although the multiple-input OR-gate circuit of FIG. 2 represents a substantial improvement over that of FIG. 1, the circuit of FIG. 2 is not ideal and several disadvantages are generally inherent in the configuration.